The present invention relates to a semiconductor memory device and to the technology useful for fabricating, for example, a bipolar CMOS static random access memory (which will be termed "bipolar CMOS RAM" hereinafter) consisting of bipolar transistors and CMOS circuits.
As a method of making a faster static RAM, the word line division system has been developed in which word lines constituting a memory array are arranged dividedly.
As shown in FIG. 13, a conventional static RAM based on the word line division system has its memory array made up of, for example, eight divisional memory arrays ARY1-ARY8 disposed on both sides of an X address decoder XDCR. The X address decoder XDCR includes decoding NOR gates NOG23-NOG25 of q in number having their input terminals supplied with complementary internal address signals ax0-axi (in this specification, an internal address signal, e.g., ax0, in phase with an external address signal, e.g., AX0, and an internal address signal, e.g., ax0, in opposite phase with AX0 are termed ax0 comprehensively) in certain combinations. The decoding NOR gates provide their output signals as row selection signals to the divisional memory arrays ARY1-ARY8 over row selection signal lines (main word lines) MW1-MWq.
The divisional memory arrays ARY1-ARY8 each include n sets of complementary data lines D1, D1-Dn, Dn, divisional word lines SW1-SWq of q in number arranged orthogonally to these data lines and in parallel to the main word lines, and memory cells MC of q.times.n in number disposed at intersections of the word lines and complementary data lines. In each divisional memory array, the divisional word lines SW1-SWq are connected with the output terminals of corresponding AND gates AG1-AG3 or AG4-AG6 of q in number. Each AND gate has one input terminal connected with a corresponding row selection signal line MW1-MWq and another input terminal connected commonly with one of block selection signal lines B1-B8 corresponding to the array. Each divisional memory array has one of divisional word lines SW1-SWq selected when the corresponding row selection signal line is selected and the associated divisional memory array (ARY1-ARY8) is designated by the block selection signal line (B1-B8).
As described above, in a static RAM having divisional word lines, memory cells MCs are not connected directly to the row selection signal lines MW1-MWq, and therefore the load capacitance coupled with each row selection signal line is relatively small. Furthermore, each divisional word line (SW1-SWq) is coupled with only n memory cells MCs in a divisional memory array, and its load capacitance is also relatively small. The number of divided memory arrays, i.e., number of divisions of the memory array, is chosen so that the total load capacitance of the row selection signal lines and divisional word lines is minimal. In consequence, the load to the decoding NOR gates NOG23-NOG25 in the X address decoder XDCR and AND gates AG1-AG6 in the divisional memory arrays ARY1-ARY8 is reduced as the whole thereby to speed up the word line selecting operation.
The foregoing word line division system is described, for example, in publication DIGEST OF TECHNICAL PAPER, p.59, published in Feb., 1983 by International Solid-State Circuit Conference.